DefSim Credits

DefSim Package is a result of efforts of a large team of people coming from several institutions:

Warsaw University of Technology (WUT) – Research work, IC and board design, firmware, drivers.
Tallinn University of Technology (TUT) – Research work, prototype software, exercises.
Slovak University of Technology (FEI STU) – Research work and BICM for IDDQ testing.

Testonica Lab – Server software, graphical user interface, package integration.

The financial support came in part from the European Union project IST 2000-30193 REASON, Polish State Committee for Scientific Research (project No. 4 T11B 023 24), and Estonian Science Foundation grants G5649, G5910.

The DefSim hardware was developed using software tools from Cadence Design Systems.
Built-in Current Monitor (BICM) design is a property of Q-Star Test company (www.qstar.be).

Testonica Lab appreciates the work done by all the people
related to the DefSim Project and REASON WP9.